| Titre : | High level power analysis an optimization |
| Auteurs : | Anand Raghunathan, Auteur ; Niraj R. Jha, Auteur ; Sujit Dey, Auteur |
| Type de document : | texte imprimé |
| Editeur : | Boston : Kluwer Academic publishers, 1998 |
| ISBN/ISSN/EAN : | 978-0-7923-8073-3 |
| Format : | 1 vol. (XVI-175 p.) / ill. / 24 cm |
| Note générale : | Bibliogr. Index |
| Langues originales: | |
| Index. décimale : | 621 (Physique appliquée) |
| Catégories : | |
| Mots-clés: | Optimisation Energie électrique |
| Résumé : |
High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies. |
| Note de contenu : |
Sommaire: List of Figures. List of Tables. Preface. 1. Introduction. 2. Background. 3. Architecture-Level Power Estimation. 4. Power Management. 5. High-Level Synthesis for Low Power. 6. Conclusions and Future Work. References. Index. |
| Côte titre : |
S8/61204 |
Exemplaires (1)
| Cote | Support | Localisation | Disponibilité |
|---|---|---|---|
| S8/61204 | Livre | Bibliothèque centrale | Disponible |
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