| Titre : | Guide to computer processor architecture : a RISC-V approach with high-level synthesis |
| Auteurs : | Bernard Goossens, Auteur |
| Type de document : | texte imprimé |
| Mention d'édition : | 1st ed |
| Editeur : | Switzerland : Springer, 2023 |
| ISBN/ISSN/EAN : | 978-3-031-18022-4 |
| Format : | 1 vol. (XXV-438 p.) / ill. col. / 24 cm |
| Langues: | Anglais |
| Index. décimale : | 004.22 (Architecture des ordinateurs) |
| Catégories : |
Ouvrages > Généralités (ouvrages généraux), information, informatique > Informatique |
| Mots-clés: | Load-store architecture. Reduced instruction set computer. Floating-point instructions. |
| Résumé : |
The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore).Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board (such a board can be freely obtained from the Xilinx University Program targeting the university professors).The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators. |
| Note de contenu : |
Contents: - Part I. Single core processors. - 1. Getting Ready. - 2. Building a RISC-V Processor. - 3. Building a Pipelined RISC-V Processor. - 4. Building a RISC-V Processor with a Multi-cycle Pipeline. - 5. Building a RISC-V Processor with a Multiple Hart Pipeline. - Part II. Multiple core processors. - 6. Connecting IPs. - 7. A Multi-core RISC-V Processor. - 8. A Multi-core RISC-V Processor with Multi-hart Cores. |
| Côte titre : |
S8/90609-90610 |
Exemplaires (2)
| Cote | Support | Localisation | Disponibilité |
|---|---|---|---|
| S8/90609 | Livre | Bibliothèque centrale | Exclu du prêt Exclu du prêt |
| S8/90610 | Livre | Bibliothèque centrale | Exclu du prêt Exclu du prêt |
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